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Chapter 2: What’s New in PlanAhead Software
Package View Legend and Spreadsheet Manipulation
A new legend to the Device and Package view allows you to view or hide specific layers
and objects, and provides a legend for layer colors and pin shapes.
The spreadsheet-like Package Pins view can be edited, sorted, flattened, and filtered for
better visibility on multifunction pins.
Alternate Part Definition
PlanAhead release 13 has the ability to define alternative parts to a design (for Virtex-5,
Virtex-6, and Spartan-6 devices only). Some restrictions apply to Spartan-6 LX25 and
LX25T devices, which is detailed in:
http://www.xilinx.com/support/answers/34885.htm .
New Pin Assignment and Banking Rules
The new pin assignment and banking rules are documented in Appendix B, DRCs, of the
PlanAhead User Guide (UG632), and include VCCaux reporting for Virtex-6 and newer
devices.
Write I/O STANDARDs to Exported UCF
PlanAhead now has the option to write out all I/O STANDARD constraints to an exported
UCF file with the File > Export > Export I/O Ports command.
New and Modified Design Rule Checks
The following is a list of the new and modified Design Rule Check (DRCs) in PlanAhead
release 13.
Attribute DRCs
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AVAL—Checks for invalid attribute values on Netlist instances.
ADEF—Checks for undefined attribute values on Netlist instances.
Bank DCI Cascade DRC
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DCICIOSTD—Checks that the DCI Cascade constraint is legal.
Bank I/O Standard DRC
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VCCAUX2—Warns of any requirements on LVPECL_33 and TMDS_33.
ChipScope DRCs
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CSUC—Checks for unconnected channels on ILA cores.
CSCL—Checks for non-clock nets that are clocking the capture of probed nets.
CSBR—Checks if device block RAM resources exceeded.
36
www.xilinx.com
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.2)
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